| PART |
Description |
Maker |
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| R2705E |
27.195MHz FSK Radio Data Receiver for Manchester Data Format
|
List of Unclassifed Manufacturers
|
| M13S5121632A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| HI-8787 |
(HI-8787 / HI-8788) 16-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT
|
Holt Integrated Circuits
|
| HI-8788PQTF HI-8787 HI-8787_06 HI-8787PQI HI-8787P |
ARINC INTERFACE DEVICES 16 bit parallel data converted to 429 & 561 serial data out
|
HOLTIC[Holt Integrated Circuits]
|
| HI-878306 |
ARINC INTERFACE DEVICE 8 bit parallel data converted to 429 & 561 serial data out
|
Holt Integrated Circuits
|
| NT5DS4M32EG-6 NT5DS4M32EG NT5DS4M32EG-5 NT5DS4M32E |
1M 】 32 Bits 】 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL
|
NANOAMP[NanoAmp Solutions, Inc.]
|
| MC68HC908JB12 MC68HC908JB12DW MC68HC908JB12JDW MC6 |
Addendum to MC68HC908JB16 Technical Data
This section updates data sheet information and introduces the 20-pin SOIC
|
FREESCALE[Freescale Semiconductor, Inc]
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
